A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

نویسندگان

  • Koh Johguchi
  • Yuya Mukuda
  • Ken-ichi Aoyama
  • Hans Jürgen Mattausch
  • Tetsushi Koide
چکیده

A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm2 (13.9μm2/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.

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عنوان ژورنال:
  • IEICE Electronic Express

دوره 4  شماره 

صفحات  -

تاریخ انتشار 2007